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ALTERA cyclone EP1C6Q240 FPGA evaluation board

ALTERA cyclone EP1C6Q240 FPGA evaluation board

SDRAM 128Mb, 143Mhz

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Nhà sản xuất: Altera

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The product introduction.
RCII - CY1C6 development board FPGA development board NIOSII development board FPGA evaluation boards, is a ALTERA cyclone EP1C6Q240 based on FPGA development platform, send ByteBlasterII download cable.USB1.1 board has USB2.0 and serial interface, and VGA, PS2 and LCD interface, supporting QuartusII and NIOSII IDE development software, excellent FPGA development board.

The products feature:
1 NIOSII support,
USB2.0 interface, 2 480Mbps provides data transmission speed, can be used as a algorithm and high speed data acquisition boards,
3 provide interfaces for the expansion, rich, video and audio applications such as the wireless network and provide reference for design,
4 with the board of the Core provide rich design, website IP will provide the upgrade Core IP version and the latest IP Core.
5 faces the domestic and foreign customers, but independent of development-oriented customize user/or expanded plate, meet the specific application

The applicable people.
Applicable to the computer professional and electrical science class specialized undergraduate and graduate student, PhD, IC integrated circuit/IP CORE prophase design verification, the relevant scientific research institutes, such as the computer science, micro electric
Son, communication, measure and control technology and instrument, electrical engineering, mechanical and electrical integration, automation or related majors, Ministry, the ministry of communications, image/r &d...
Red hurricane II and development board is not only the SoPC college graduate and undergraduate annual competition, is the most ideal mentor successfully developed various institutes characteristic of new products best choice

The list of products.
1 FPGA development board
2 ByteBlasterII download cable
3 serial connection
4 USB cable
5 5V, power 1. 1A
6 standard 16 x2 LCD module 1
7 supporting DVD 1

The 1C6 RC2 - hardware configure development board.
With 4 layer board industry standard elaborate design:

1 FPGA chip: EP1C6Q240 5, about 15 million laiton scale.
2 configuration EPCS1: chips
3 512K high-speed, asynchronous an SRAM an uploaded file
One of the ASRAM 256K 16Bit x, independent byte enables signal
4 SDARM 128Mb expressway
A SDRAM 32Bit x 4M, highest speed 143MHz literacy,
5 4M an uploaded file fast FLASH
A 8Bit x x 4M 2M 16Bit Flash or reading speed for 90ns,
Flexible page mode, can be used to store the FPGA configuration files or operating system image files,
6 and needle rs-five 232 serial port
The data communication with computers,
Auxiliary debugging, output,
7 PS / 2 mouse and keyboard interface
The mouse and keyboard interface standards, support and 3.3 V equipment, can be used to verify 5-v PS / 2, realize the interface protocols a IO devices expanded,
8 8 color VGA interface
Direct VGA display docking, 8 colors shows, For the verification VGA timing,
9 USB1.1 interface experiment
To expand the FPGA IO directly used to evaluate the USB interface, on FPGA realizing USB IP nuclear performance,
10 USB2.0 high speed data interface
Used widely, performance and stability of Cypress CY68013A chip company realized the USB interface, computer can realize high speed data transfer between,
11 LCD interface
The standard type LCD module interface, character provided 16 x2 characters of control method and the driver,
12 function expansion interface
Through the corresponding expanded plate, Audio and Video, can realize network applications.
The user can also develop their definition of the interface.

The experimental result shows.
1 the PS / 2 interface keyboard transmission experiment
PS / 2 is the PC and many industrial control platform of standard user input devices, teaching platform provides a standard interface, the PS / 2 mouse can support. / keyboard This experiment can through the teaching platform for a PS / 2 interface input from the keyboard operation information, data output will be RS232 interface to a PC.
2 VGA interface experiment
Each color has three colors respectively, red, green and blue. R, G, B signal different combinations can show 8 colors as shown in the diagram below.
3 USB2.0 interface experiment data transmission
USB protocol is now widely used in high speed data transmission standards, teaching platform provides a standard interface for support, high-speed USB2.0 high capacity data transmission fields of application development. The experiments show USB2.0 interface and PC through high-speed communication effect.

The supporting software.
1 NiosII development tools, including
> NisoII integrated development environment (IDE 7.2)
> GNU tools
> NiosII instruction simulators (ISS).
2 the permit with Micro uC/OS - II real-time operating system and uCLinux on
3 LightWeightIP TCP/IP stack
4 QuartusII design software, 7.2 version of the patch, support the + SP2 series CycloneI/II chip,
5 the SoPC Builder standard microprocessor peripherals
6 Microtronix setups, NiosII Linux versions, support QuartusII7.2 and 1.4 NiosII 7.2
7 the FPGA/ASIC design resources, including textbooks, code, and more than 1GB reference design etc

The design documents.
1 development board user manual
2 development board diagram (PDF)
3 QuartusII and NIOSII IDE installation guide and how-to tutorials
4 Verilog HDL/VHDL experiment teaching guideline
5 NIOSII embedded system L experimental teaching guideline
4 main chip data manual and simulation model (HDL language description model for system simulation),

The hardware design examples of HDL.
directory
Preface to 1
The first chapter ALTERA QUATUSII 5.0 introduces three use
1 Outlines 3
2 QUATUSII design process
3 to establish 5
4 establish design 6
QUATUSII EDITOR which established ammeters use principle chart files
Use TEXT EDITOR 2.2.2 QUARTUS II
Use VERILOG HDL, 2.2.3 and 9. AHDL VHDL
3 compile comprehensive design
4 simulation project 11
5 distribution equipment and pipe 13 feet
6 procedures download 16
7 and the use of logic analyzers software
2 sets trigger 19
The second chapter of digital circuit experiment with digital systems
The first part of the experiment of 20
Experiment a 3/8 decoder 20
Lab 2 prescaler 23
Based on the experimental three LPM nuclear sine function generator 25
The second part interface control experiment 37
Experimental four LCD display experiment 37
Experimental five rs-five 232 serial controller 40
Experimental six VGA output control experiment 44
Experimental 7 PS / 2 keyboard controller experimental 46
Experimental eight interface interconnect experimental 50
In the third part of the comprehensive experimental 52
Comprehensive experimental 52. 14 experiment

[NIOSII design examples.

The first part NIOSII use 2
1 NIOSII introduce 2
2 NIOSII design process
The second part NIOSII computer experiment
Experiments NIOSII a development process instance, LED display
Lab 2 standard NIOSII hardware components and systems
Lab 3 - JTAG host and realize UART of communication between the FPGA 46
Experimental four SYSTEM ID experiment 49
Experimental five realization of serial communication 51
Experimental six realize LCD display 55
Experiment with the seven key trigger counter 57
8 simple experiment digital clock 60
Nine FLASH function test testing 62
Experiments NIOSII ten experiment

The CD supporting examples.
1 and decoder
2 and decoder
3 prescaler
4 waveform generator
5 LCD display
6 LCD display (VHDL)
7 serial experiments
8 VGA striped experiment (8),
9 VGA experiment (graphics)
10 to PS2 LCD
11 PS2 c.k. RS232
12 the comprehensive test
13 4 * 4 matrix keyboard experiment
14 buttons, dial the code switch
15 USB IN
16 USB OUT
17 LED lamp water
18 for 7 digital tube
19 reading test. An SRAM

The Demonstrations.
1 the Audio Audio
2 10M and 100M
USB2.0 3
4 Video Video
5 basic experiment

The other design examples.
1 USB2.0 interface chip and PC communications examples
2 video collection and output chip configuration examples
More design examples of browsing website.

The optional expanded plate.

1 10M network expansion board .
Adopted widely RTL8019 as interface control chip, provide 10M network interface, satisfies most web applications.
Provide complete SOPC components and UC OSII/next device drivers, and provide the Altera Webserver and SimpleSocket examples

2 the audio input/output expansion board .

3 video input/output expansion board
Adopted widely SAA7113 and SAA7121 chip, video signal acquisition and output. Input/output interface using universal AV interface.
Provide Video Loopback test procedure and superposition character procedures.

4 100M network expansion board
Using 10M / 100M Ethernet physical/medium access control (MAC and PHY /) chip LAN91C111, compatible Altera original development board network interface and design examples.

5 USB cable Blaster download.
UClinux debugging to download the kernel and burning flash, if the ByteBlasterII cable, slowly, so we recommend you use USB cable Blaster

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